1. Field of the Invention
The present invention is directed toward the field of building custom memory systems cost-effectively for a wide range of markets.
2. Art Background
Dynamic Random Access Memory (DRAM) is the most popular type of volatile memory and is widely used in a number of different markets. The popularity of DRAMs is mostly due to their cost-effectiveness (Mb/$). The PC main memory market has traditionally been the largest consumer of DRAMs.
The DRAM interface speed in several important markets is increasing rapidly. For example, the PC market today uses 667 MHz DDR2 SDRAMs. The industry is on track to use 800 MHz DDR2 SDRAMs in 2006. Effort is also underway in developing DDR3 SDRAMs that are expected to have interface speeds ranging from 800 MHz to 1600 MHz.
Signal integrity becomes increasingly challenging as the interface speed increases. At higher speeds, the number of loads on a memory channel must be decreased in order to ensure clean signals. For example, when the PC desktop segment used 133 MHz SDRAMs, three DIMM slots per memory channel (or bus or interface) was the norm when using unbuffered modules. When this market segment adopted DDR SDRAMs and now DDR2 SDRAMs, the number of DIMM slots per memory channel dropped to two. At DDR3 speeds, it is predicted that only one DEWM slot will be possible per memory channel. This obviously places an upper limit on the maximum memory capacity of the system.
Clearly there is a need for an invention that increases the memory capacity of a system in a manner that is both cost-effective and compatible with existing and future standards while solving various technical problems like signal integrity.